LogNIC-micro23.pdf

Background

• Parser: Parses the packet headers for match-action processes that happens in next module
• Traffic Manager: has queues connected to each IP (Intellectual Property) and does scheduling
  • Pipeline NIC
  • Many core NIC
  • RMT NIC
• Bypass Path: if the packet does not need significant processes can just be sent to deparser
• Recirculation Path: if the packet needs more processing, can be sent back to the start

Why do we need a Performance Model:

• Need thorough understanding of vendor-specific SmartNIC hardware:
  • Actual throughput of a SmartNIC off-chip compression engine depends on:
    • Execution parallelism
    • Aggregated interconnect bandwidth between NIC cores and accelerator
    • Delivery rate of submission/completion signals
• Need careful refactoring in application logic across heterogeneous computing engines, on/off chip interconnects and memory subsystems
  • models so far did not consider the differing bandwidths of different interconnects between different modules (e.g. ingress interconnect vs IP to IP interconnect)
• Need to dissect relationship between SmartNIC execution behavior and traffic
  • models so far considered traffic to be constant

LogNIC Model:

Hardware Model of SmartNIC:

• A single interface that connects Ingress/Egress Engine and that connects IP to each other and to main memory system
• Memory subsystem with an interface shared by IPs, DRAM, scratchpad, SRAM, and TCAM

IP Architecture:

• m input queues, request scheduler, and n parallel execution engines