Wafer Bonding Method

→ cavities created on substrate before bonding

→ required plate bonded over cavities in a vacuum environment

⇒ Most common technique: fusion bonding

• thermal oxide layer is grown on conductive silicon substrate

• cavities are formed by etching this oxide layer, leaving oxide posts around the cavities

• second oxidation creates insulating layer required for proper CMUT operation

  • oxide posts bonded to device layer of an SOI wafer
  • handle and BOX layers removed
    • leave plate which serves as vibrating structure and top electrode of device

• distance between cavities can be reduced

  ⇒ fill factor increased

  ⇒ sufficient bonding surface should be left

NOTE: Fusion bonding has low tolerance of surface roughness and contamination

⇒ Anodic Bonding

high tolerance to surface roughness and contamination

outgassing during bonding ⇒ trapped gas in cavity

chemical etching and used buffered oxide etch (BOE) to etch borosilicate substrate

1. before etching, photoresist was hard-baked for 1 hour in order to improve the adhesion between the photoresist and the substrate

1. etch time divided into 3 min slots (to prevent peeling of resist) & hard baked for 10 mins

   • etch depth of 230nm
   • surface roughness of 0.8nm
   • undercut made in lateral etch (easing lift-off)

   

2. after etching, photoresist not removed and put in evaporation chamber for metal deposition

   1. 20nm chromium
   2. 90nm metal
   3. gap height determined by difference between deposited metal thickness and etch depth of cavity

   

3. deposit Silicon Nitride on device layer of SOI

   1. intermediate bonding layer
   2. insulating layer to prevent electrical shorting in collapse mode
   3. deposition of 200nm PECVD silicon nitride on SOI wafer

   

4. test bonding at various voltages (high to low)

   1. 700V when no damage on gold and still achieve high bonding yield

   

5. After bonding: handle wafer ground down to 100 micro m and rest was removed using heated tetramethylammonium hydroxide

   

6. Upward deflection due to pressured gas inside cavities after bonding

   1. second lithography and etch silicon over the bottom electrode pad in order to evacuate the gas
   2. photoresist removed by oxygen plasma
   3. wafer placed back into PECVD chamber to seal cavities at bottom pad location
      1. 800nm conformal silicon nitride was deposited (3 times higher than cavity depth)

   

   

7. Electrical Contact Pads

   1. silicon nitride over plate and pad removed by masking sealing location
   2. third and last patterned photoresist layer is also used for lift-off purpose to deposit metal over bottom pad and over silicon plate for better conductivity